Phase Lock Loop Design Program PLLDES.BAS This is the combination of two programs: PLLPAS.BAS, which designs a type 1 PLL using a passive filter and PLLACT.BAS which designs a type 2 PLL using an integrator filter. The type 2 PLL consists of: mixer or demodulator, integrator, and oscillator. This type has zero phase error in the steady state and is useful for recovering a pilot tone or carrier frequency. The mixer gain is measured in volts per radian. The maximum swing at 90 degrees will normally define the gain: Kd=MRV/(PI/2) The integrator gain is determined by the RC: Kf=1/(R*C) The oscillator gain is measured in Radians per sec per volt. Since the oscillator parameter is usually given as OS=Hz/volt, the oscillator gain is: Ko= OS*2*PI. You can diagram this design problem with a straight edge and semi-log paper: At one radian per second (.159Hz), the open loop gain is the product of the three constants: Aol=Kd*Kf*Ko = MRV*OS*4/(R*C). This establishes a point on a curve of log gain versus log freq. The zero dB frequency is up or down this curve by 40dB/decade. The case of a passive filter which rolls off at 20 dB/decade up to a point, is covered later in this article. If 20*log(Aol) = DB, then DB/40 = fraction of a decade above or below .159Hz .159*10^(DB/40) = zero dB frequency An optimum (no overshoot) design is desired, which means that the curve should pass through zero dB at 20dB/decade. To accomplish this, a lead must be put at a frequency (F1) lower than F3. And, to filter the ripple going into the oscillator control port, a lag is introduced at a higher frequency (F2). Since the integrator has AC gain = R2/R1, then R2 should be as small as possible, which means F1 is at a high Frequency. Also, F2 should be at as low a frequency as possible in order to be a good ripple filter. Unfortunatly, this phase lock loop has an inherent phase overshoot which is inversly proportional to the ratio F2/F1, see below. The ratio of recovery time to rise time is proportional to F2/F1. Minimum overshoot versus F2/F1 F2/F1 % OVERSHOOT 30 9 60 5 100 3.2 200 1.5 400 .6 800 .2 Note that if KF is large enough that the integrator reaches max DC open loop gain between F1 & F2, this analysis will be in error. Here is the proceedure: 1. Draw a line thru the zero dB frequency (F0) at 20db/decade. The zero dB frequency depends on the desired bandwidth (BW): F0 = BW*(.038*LOG(F2/F1)+.672) Choose F2/F1 from the chart above. 2. Find F1 from this equation: F1 = F0/(.2805*(F2/F1)+1.25) 3. Draw a line thru F1 on the first line at 40dB/decade until it intersects the zero dB line. This is F3. Since Kd and Ko are usually known, then: Kf = ((2*PI*F3)^2)/Kd/Ko 4. Choose C1, then R1 = 1/Kf/C1 and R2 = 1/2/PI/F1/C1 R3 = 1/2/PI/F2/C2 Now consider the case of the PLL that uses a low pass filter instead of an integrator. Since there is only one integrator in the loop, it is a type 1 servo which has phase error dependent on the deviation of the oscillator from zero control volts, but has no frequency error in the steady state. This type is most useful as a frequency discriminator or FSK demodulator. The filter gain is unity (Kf=1) so the open loop gain is: AOL = Kd*Ko. And, since the rolloff is 20db/decade, F3 = .159*AOL Using the desired bandwidth (BW) as reference, the upper frequency cut is determind experimentally to be: F2 = BW/1.28 Putting F2 up on the 20dB/decade slope by 10dB will give a pulse response with no noticable overshoot. To find F1 mathematically, note that: F1 = F3/(10^(DB/20)) = F2/(10^((DB-10)/40)). Where DB is the loop gain at F1. Or, with straight edge and semilog paper follow this proceedure: 1. Draw a line thru F3 on the zero dB line at 20dB/decade. 2. Draw a line thru F2 on the +10dB line at 40dB/decade until it intersects the first line at F1. Now choose C1 and find: R1 = 1/2/PI/F1/C1 R2 = 1/2/PI/F2/C1 A second capacitor to filter high frequency ripple should be added at the oscillator input. Its value is: C2 = C1/100. The lock range, taken from the National application note AN46: Flock = 1.41*SQR(2*BW*KO*KD-BW^2) approximately Also, referring to AN46, I find the damping factor (Zeta) to be .88 and the maximum frequency step at the input, that will throw the loop out of lock, is: Fmax = .625*SQR(KO*KD/R1/C1) Now is is desirable to make a SPICE model for the phase lock loop in order to check the response. The problem is that modeling a VCO and mixer or demodulator is complex and results in a long simulation. The approach used here is to omit the carrier frequency and just model the error loop. The mixer is modeled as an operational summer and the oscillator is an operational integrator. The voltage at the oscillator model input is just the error voltage, do not expect to see the modulation because there is no carrier. The voltage at the oscillator model output is the oscillator phase in radians. The input voltage to the demodulator model represents a phase deviation of the input carrier. If the difference between the input and output exceeds PI/2 volts, the model is no longer valid because the real device will go out of lock, but the model cannot. To measure the modulation bandwidth, the oscillator can be modulated at at its input and the resultant feedback monitored at the filter output. The type 1 model circuit is shown in Figure 1. RD is equal to the demodulator gain (Kd) in Kohms. C3 is chosen to make the integrator gain equal to Ko: C3 = 1/KO/R7. The inverter, EFB, is needed to make the feedback phase correct. The capacitor C2 is an optional high frequency bypass which is recommended to reduce jitter in the oscillator, but which will have little effect in the model. The type 2 model circuit is shown in Figure 2. It is the same as the type 1 circuit except for the integrator filter. Note that a capacitor could have been placed across R2 instead of using R3 and C2, but the capacitor across R2 is only effective up to the bandwidth limit of the amplifier. After that, it couples ripple into the oscillator. END